1. Field of the Invention
The present invention relates to a semiconductor device having a fan-out structure and a manufacturing method thereof.
This application is counterpart of Japanese patent application, Serial Number 399373/2003, filed Nov. 28, 2003, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
The need to scale down and thin an outer size (package size) of a semiconductor device mounted to an electronic equipment such as a portable device has been increasing in recent years. With its demand, there has been proposed a CSP (Chip Size Package) corresponding to a semiconductor device on which packaging is effected in substantially the same outer size as an outer size of a semiconductor chip.
In terms of a reduction in manufacturing cost, attention is now given, as one form of CSP, to a WCSP (Waferlevel Chip Size Package) obtained by fractionization by use of dicing or the like after processes up to an external terminal forming process have been completed in a wafer state (see a patent document 1, for example).
A further reduction in semiconductor chip has been required with respect to the demand for an improvement in the collected number of chips per wafer, and the like with a view to further scaling down a recent electronic equipment and reducing its manufacturing cost.
However, the WCSP had a fan-in structure wherein since the area of a packaging or mounting surface on which external terminals were disposed, was identical to the area of the semiconductor chip, the external terminals were disposed inside electrode pads formed in the peripheral edge of the surface of the semiconductor chip.
In the WCSP having such a fan-in structure, the number of external terminals capable of being disposed on the mounting surface is limited. Therefore, there was a need to narrow the interval, i.e., array pitch between the adjacent external terminals in order to achieve a further reduction in semiconductor chip while a given predetermined number of external terminals are being maintained.
As a result, there has been fear that since the routing of wirings from the electrode pads on the semiconductor chip to the external terminals narrow in array pitch becomes complicated, degradation in product yield and the like occur.
Therefore, there has been proposed a WCSP having a fan-out structure, wherein the area of a mounting surface on which external terminals are disposed, is made wider than that of the surface of a semiconductor chip, and the external terminals are disposed outside electrode pads formed in the peripheral edge of the surface of the semiconductor chip (see a patent document 2, for example).
It was, however, difficult to form a wiring in desired position with satisfactory accuracy in the case of the formation of the wiring subsequent to a resin encapsulating process in each WCSP described up to now. This is because it is difficult to control with satisfactory accuracy as designed, the relationship of layout between the position of a mask pattern for patterning the wiring and the positions of plural semiconductor chips.
Meanwhile, in order to ensure alignment accuracy at the superposition of a pair of semiconductor elements, there is known a configuration wherein alignment trenches are provided in opposite surfaces of the semiconductor elements (see a patent document 3, for example).
Patent Document 1
Japanese Laid Open Patent No. 2000-260733
Patent Document 2
Japanese Laid Open Patent No. 2003-258157
Patent Document 3
Japanese Laid Open Patent No. 2000-243901
Therefore, there has heretofore been a demand for mounting of a plurality of semiconductor chips on design desired positions with satisfactory accuracy prior to a resin encapsulating process upon forming a wiring in a desired position with satisfactory accuracy in a WCSP. However, the above patent document 2 does not propose such a technique specifically.
On the other hand, although the patent document 3 discloses the alignment trenches used upon superposing the semiconductor chips on one another, it does not originally belong to such a technique that the superposed plural semiconductor elements are fractionized into individual semiconductor devices, (packages). Thus, the technical aspect that the distances (intervals) among a plurality of semiconductor chips prior to a resin encapsulating process are kept like designed values with satisfactory accuracy in consideration of a wiring forming process and a fractionizing process to be executed later, does not exist in the patent document 3.